With a view to achieving higher integration and higher performance of a semiconductor device, a vertical transistor SGT has been proposed which comprises a pillar-shaped semiconductor layer formed on a surface of a semiconductor substrate, and a gate formed to surround a sidewall of the pillar-shaped semiconductor layer (see the following Patent Documents 1 and 2). In the SGT, a source, a gate and a drain are arranged in a vertical direction, so that an occupancy area can be significantly reduced as compared with a conventional planar transistor. In addition, the gate is formed to surround a channel region, so that, as a size of a pillar-shaped semiconductor layer is reduced, channel controllability of the gate can be effectively improved to obtain steep subthreshold characteristics. Furthermore, an improvement in carrier mobility based on electric field relaxation in the channel region can be expected by setting an impurity concentration and a size of the pillar-shaped semiconductor layer to allow the pillar-shaped semiconductor layer to become fully depleted. Therefore, the use of the SGT makes it possible to simultaneously achieve higher integration and higher performance as compared with the conventional planar transistor.
FIG. 177(a) shows a top plan view of a CMOS inverter designed using the SGT disclosed in the Patent Document 1, and FIG. 177(b) is a sectional view taken along the cutting-plane line A-A′ in FIG. 177(b).
Referring to FIGS. 177(a) and 177(b), an N-well 1302 and a P-well 1303 are formed in an upper region of a Si substrate 1301. A pillar-shaped silicon layer 1305 forming a PMOS (PMOS-forming pillar-shaped silicon layer 1305) and a pillar-shaped silicon layer 1306 forming an NMOS (NMOS-forming pillar-shaped silicon layer 1306) are formed on a surface of the Si substrate, specifically on respective ones of the N-well region and the P-well region, and a gate 1308 is formed to surround the pillar-shaped silicon layers. Then, each of a P+ drain diffusion layer 1310 formed beneath the PMOS-forming pillar-shaped silicon layer, and a N+ drain diffusion layer 1312 formed beneath the NMOS-forming pillar-shaped silicon layer, is connected to an output terminal Vout 7. A source diffusion layer 1309 formed in an upper portion of the PMOS-forming pillar-shaped silicon layer is connected to a power supply potential Vcc 7, and a source diffusion layer 1311 formed in an upper portion of the NMOS-forming pillar-shaped silicon layer is connected to a ground potential Vss 7. Further, the gate 1308 common to the PMOS and the NMOS is connected to an input terminal Vin 7, and the diffusion layer (1310, 1312) beneath a respective one of the pillar-shaped silicon layers is connected to the output terminal Vout 7. In this manner, the CMOS inverter is formed.
FIGS. 178(a) to 178(f) show a schematic process flow for forming a pillar-shaped silicon layer and a gate electrode in the SGT disclosed in the Patent Document 1. In FIG. 178(a), a pillar-shaped silicon layer 1401 is formed on a silicon substrate by etching. In FIG. 178(b), a gate dielectric film 1402 is formed. In FIG. 178(c), a gate conductive film 1403 is formed. In FIG. 178(d), a resist 1404 for a gate line pattern is formed to be in contact with a portion of a gate conductive film surrounding the pillar-shaped silicon layer. In FIG. 178(e), the gate conductive film 1403 is etched back to form a gate electrode 1403 and a gate line 1405 of an SGT. In FIG. 178(f), the resist is released. In the above process flow, the gate electrode 1403 is formed around the pillar-shaped silicon layer 1401 by a desired film thickness, in a self-alignment manner, so that two pillar-shaped silicon layers each having a gate electrode to be applied with a different potential can be arranged side-by-side with a relatively small distance therebetween.
However, in the above process flow, the resist 1404 must be formed to be accurately in contact with the portion of the gate conductive film around a sidewall of the pillar-shaped silicon layer, in FIG. 178(d). Therefore, a process margin in a lithography step of forming the gate line is small, which causes difficulty in stably fabricating the gate line. The following description will be made in regard to this point.
FIGS. 179(a) to 179(c) illustrate a process flow in case where the resist 1404 is positionally deviated to the right side in FIG. 178(d). FIG. 179(a) shows a state after a resist 1414 for a gate line pattern is positionally deviated to the right side during alignment of a lithographic exposure. In this state, there arises a space between the resist 1414 and a sidewall of a pillar-shaped silicon layer 1411. In FIG. 179(b), a gate etch step is performed. In FIG. 179(c), the resist is released. In this case, a gate electrode 1413 and a gate line 1415 of a resulting SGT are undesirably disconnected from each other.
FIGS. 180(a) to 180(c) illustrate a process flow in case where the gate-line resist 1404 is positionally deviated to the left side in FIG. 178(d). FIG. 180(a) shows a state after a resist 1424 for a gate line pattern is positionally deviated to the left side during alignment of a lithographic exposure. In this state, there arises an overlapped area 1426 between the resist 1424 and a portion of a gate electrode on a top of a pillar-shaped silicon layer 1421. In FIG. 180(b), a gate etch step is performed. In FIG. 180(c), the resist is released. In this case, a gate electrode 1423 of a resulting SGT undesirably has a shape abnormality 1427 on a side where the resist is formed.
A value of the above positional deviation of the resist arising from the alignment varies depending on a position on a wafer and a position in a chip, and thereby it is impossible to keep positional deviations in all patterns on a wafer, within a range free of the occurrence of the above problem. Thus, in the above SGT forming method, a process margin for forming the gate line becomes extremely small, and thereby it is impossible to produce an integrated circuit in high yield.
As one of the measures against the problem in the above SGT gateline forming method, the following Non-Patent Document 1 discloses an SGT gate-line forming method which is improved in process margin. FIGS. 181(a) to 181(g) illustrate a schematic process flow for forming a pillar-shaped silicon layer and a gate electrode of an SGT, which is disclosed in the Non-Patent Document 1. This process flow will be described below. In FIG. 181(a), a silicon substrate is etched to form a pillar-shaped silicon layer 1501. In FIG. 181(b), a gate dielectric film 1502 is formed. In FIG. 181(c), a gate conductive film is formed. In FIG. 181(d), the gate conductive film, and a portion of the gate dielectric film on a top of the pillar-shaped silicon layer, are polished by chemical mechanical polishing (CMP). In FIG. 181(e), the resulting gate conductive film is etched back in such a manner that a portion of the gate conductive film surrounding the pillar-shaped silicon layer is etched to have a desired gate length. In FIG. 181(f), a resist for a gate line pattern is formed by lithography. In FIG. 181(g), the gate conductive film is etched to form a gate electrode and a gate line.
In the above process flow, although a process margin in a lithography step of forming the gate line becomes larger, as compared with the process flow disclosed in the Patent Document 1, the gate electrode to be formed around the pillar-shaped silicon layer is not formed in a self-alignment manner, with respect to the pillar-shaped silicon layer. As a result, the gate electrode will be widely formed around the pillar-shaped silicon layer, and a film thickness of the gate electrode to be formed around the pillar-shaped silicon layer will vary depending on a deviation in alignment of a resist pattern and an error in size of the resist pattern. Thus, if a distance between two pillar-shaped silicon layers each having a gate electrode to be applied with a different potential is reduced, the respective gate electrodes will be short-circuited with each other. Therefore, an occupancy area of an SGT-based circuit is liable to become large.                Patent Document 1: JP 2-188966A        Patent Document 2: JP 7-99311A        Non-Patent Document 1: Ruigang Li, et al., “50 nm Vertical Surrounding Gate MOSFET with S-factor of 75 mv/dec”, Device Research Conference, 2001, p. 63        
As a prerequisite to achievement of an SGT applicable to a product comprising a highly-integrated and high-performance logic circuit, such as a CPU, it is necessary for a gate forming process to meet the following requirements. A first requirement is that it is capable of forming a gate electrode around a pillar-shaped silicon layer in a self-alignment manner and with a desired film thickness. A second requirement is that it is less vulnerable to a deviation in exposure alignment during gate line formation. A third requirement is that it is capable of accurately controlling a gate length to minimize a variation in gate length and increase a process margin.
In view of above problems, it is an object of the present invention to propose an SGT production method capable of solving the above problems.